Design and characteristics of 4Mb hybrid bubble memory chips

Abstract

We report the design and functional margins of a 4 Mbit hybrid bubble chip. The basic cell was scaled down from 4 × 4 µm to 4 × 3.6 µm. Thus the die size is of 10.1 mm × 10.1 mm so that existing package can be used. The chip is divided into four 1 Mbit blocks with an access time of 10 ms and a data rate of 400 Kbaud. Functional margins and temperature dependance are presented for hybrid loops and gates. Hybrid generation requires a nucleation current 30 mA less than a conventionnal pickax generator. Detector produces 7 mV/mA with good temperature characteristics. An Overall 30 oe bias field margin was achieved for a 100 kHz 50 oe drive field.