Design and analysis of VLSI-based parallel multipliers

Abstract

A design of a parallel multiplier is presented in which the time-consuming multiplication process is recursively decomposed into simple summation processes that can be executed simultaneously. At each recursive step, each multiplier and multiplicand is partitioned into four groups of bits and produces 16 partial product terms. An efficient summation process of adding up these partial product terms is proposed. These terms are grouped in accordance with their relative bit positions and with the use of three-to-two counters. Based on the proposed summation process, the multiplier can achieve a speed complexity of order O(log2n). Owing to its regular structure, the proposed parallel multiplier is feasible for VLSI implementation. In the paper, the designs of parallel multipliers implementing various orders of partitions are also studied. The results show that partitioning each multiplier and multiplicand into five groups of bits can generally yield a higher speed performance with less chip area for arbitrary bit size.