Design and analysis of ternary delay flip-flop implemented with carbon nanotube field effect transistor

Abstract

Flip-flops serve as fundamental memory storage elements in digital circuits, and their efficiency significantly affects overall circuit performance. The aim of this study is to create a D flip-flop based on ternary logic and evaluate its performance in comparison to flip-flops that have already been designed. The proposed D flip-flop design leverages Carbon Nanotube Field Effect Transistors (CNTFETs). CNTFETs offer unique properties that can enhance the speed and power efficiency of flip-flop design. To evaluate the performance of the proposed design, it was simulated using the HSPICE simulator with a 32 nm Stanford CNTFET model. The simulation parameters include a power supply voltage of 0.9 volts and an operating frequency of 1 GHz. These specific settings allow researchers to analyze the behavior and performance of flip-flops under realistic operating conditions. By comparing the simulation results of the proposed D flipflop with the performance of previously designed flip-flops, the improvements are assessed in terms of the speed and power consumption. The simulation results provide valuable insights into the efficiency, reliability, and responsiveness of the proposed design. The findings of this research contribute to the advancement of digital circuit design by introducing a novel D flip-flop based on ternary logic and CNTFET technology. The goal is to enhance the overall performance efficiency of digital circuits, particularly in applications where D flip-flops are used as building blocks such as shift registers.