Design and Analysis of Self-write-terminated Hybrid STT-MTJ/CMOS Logic Gates using LIM Architecture

Abstract

Among all spintronics devices, spin transfer torque (STT) magnetic tunnel junction (MTJ) is the most promising candidate for logic-in-memory (LIM) architecture. It alleviates the performance degradation observed in the present CMOS circuits which are built using standard von-Neumann architecture. However STT-MTJ suffers the issues such as switching delay due to stochasticity as well as wastage of write power. Hence, in this work continuous monitoring and self-write-termination (SWT) process is adopted for STT-MTJs and studied the performance of all the logic gates; AND/NAND, OR/NOR and XOR/XNOR developed using LIM architecture. Investigation of the read/write power, read/write delay, read/write power delay product and transistor count of SWT-STT-MTJ/CMOS logic gates are performed and compared them with its conventional counterparts. Further, Monte-Carlo simulations are also conducted to study the behavior of hybrid logic gates for variations that could occur during fabrication. The simulation results reveal that SWT-STT-MTJ/CMOS logic gates dissipates lower power, PDP and produce quicker output response.