Abstract
As technology scales, a lower supply voltage means transistors in ring oscillators frequently switch between triode and saturation. A model based on random mid-point voltage is developed in this brief. It reduces the number of first-passage time calculations. For instance, when applied to a current-starved inverter delay cell, the number of calculations is reduced from 5 to 1. Moreover, when applied to a differential pair delay cell, new design insights develop. These insights result in improved phase noise (PN) via a combination of reduced input pair size and the addition of extra poly capacitance at the output. Measured PN on oscillators fabricated in 0.18-μm CMOS, which oscillate at 448 and 473 MHz, shows an improvement of 6 dBc/Hz. In both types of delay cells, the model agrees reasonably well with measurement results.
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