Abstract

True Random Number Generators (TRNGs) became the basic building block of modern cryptography. Though most of the noise source of TRNGs is analog circuit, to provide compactness and high throughput, hardware based TRNG solutions are recommended. This work aims at the generation of true random bits through beat frequency detection influenced by identical length of ring oscillators on FPGA. The main idea of this work is to extract the true randomness from one jitter clock produced by a ring oscillator through another jitter clock generated by the second ring oscillator. To enhance the randomness, Von Neumann Corrector (VNC) post processing is utilized. Proposed TRNG is designed using VHDL and Quartus II 8.0 EDA tool. It consumes 523 combinational functions and 539 logic registers on Altera Cyclone II EP2C20F4S4C7 FPGA where it achieves the throughput of 26.640650 Mbps when 27 MHz is used as sampling clock. Statistical efficiency of the TRNG is evaluated using entropy, correlation and NIST SP 800 -22 analyses. True randomness of the TRNG is verified through restart experiment.

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