Design and analysis of monolithic triple-stacked power amplifiers using GaAs HBT-HEMT process

Abstract

This paper describes design and analysis of monolithic triple-stacked power amplifiers (PAs) in 2-μm / 0.5-μm GaAs HBT-HEMT process. The proposed PAs are designed using both heterojunction bipolar transistor (HBT) and high electron-mobility transistor (HEMT). Based on a common-emitter (CE) configuration of HBT with stacked common-gate (CG) configuration of HEMTs or stacked common-base (CB) configuration of HBT as the third-stacked transistor, better power performances with good PAEs can be achieved as compared with the CE or common-source (CS) amplifier due to high output stacking impedance. The bandwidth with HEMT/CG configuration as the third-stacked transistor is investigated. The proposed stacked PAs demonstrate a maximum output powers of 31.7dBm, a compact chip size of within 1.6×1mm2, and a maximum power added efficiency (PAE) of 38.3% at 5GHz.