Design and Analysis of Low-Power 16-bit Parallel-Prefix Adiabatic Adders

Abstract

Adders are the elementary components of all the general-purpose microprocessors and signal processing units which include filters, MAC, Arithmetic Logic Unit, … The efficient design of an adder determines the overall performance efficiency of the system. Parallel Prefix Algorithm is one of the proficient way of implementing an adder. The increase in the number of portable devices has increased the need for low power design techniques. Adiabatic Logic is the one of the promising technique to recover and recycle the power back to the source. This work provides a comparison in terms of area, power and latency between Adiabatic Ripple-Carry adder (RCA), Kogge-Stone Adder (KSA) and Han-Carlson Adder (HCA) and their Static CMOS counterparts. CMOS 180 nm technology is used for schematic entry. Functional verification is performed using Cadence Virtuoso - Spectre Simulator. Analysis of the adders shows that Adiabatic KSA has the least latency, whereas Adiabatic HCA provides a good trade-off between latency and power dissipation.