Design and Analysis of Low-Voltage and Low-Power 19T FinFET-TGDI-Based Hybrid Full Adders

Abstract

This paper proposes two 19 transistor (19T) hybrid adder designs based on Fin Field Effect Transistor-Transmission Gate Diffusion Input (FinFET-TGDI) technique. The performance of these designs is compared with various state-of-the-art adders, and the simulations are carried out using 18[Formula: see text]nm FinFET technology in the Cadence Virtuoso tool at a supply voltage of 0.8[Formula: see text]V and nominal temperature. Results show that the proposed adders outperform the conventional Mirror adder, achieving a 25% improvement in maximum propagation delay, a 20% improvement in average power, and a 39% improvement in Power Delay Product (PDP). Both proposed adders also demonstrate significant benefits in terms of Figure of Merit (FoM) when compared with other reported architectures. The simulations also consider variations in the nominal supply voltage of 10% and temperature variations from −55[Formula: see text]C to 125[Formula: see text]C for the PDP of all adders. Furthermore, the post-layout simulation results for both proposed adder architectures under nominal supply voltage are presented. To assess the robustness of the circuits, process corner analysis and Monte Carlo analysis are performed for all adder architectures.