Abstract
Recently, double-gate MOSFETs (DGMOSFETs) have been shown to be more optimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS. However, DGMOSFETs for subthreshold circuit design have not been much explored in comparison to those for strong inversion-based design. In this paper, various configurations of DGMOSFETs, such as tied/independent gates and symmetric/asymmetric gate oxide thickness are explored for ultra-low power and high efficient radio frequency identification (RFID) design. Comparison of bulk CMOS with DGMOSFETs has been conducted in ultra-low power subthreshold digital logic design and rectifier design, emphasizing the scope of the nano-scale DGMOSFET technology for future ultra-low power systems. The DGMOSFET-based subthreshold logic improves energy efficiency by more than 40% compared to the bulk CMOS-based logic at 32 nm. Among the various DGMOSFET configurations for RFID rectifiers, symmetric tied-gate DGMOSFET has the best power conversion efficiency and the lowest power consumption.
Highlights
One of the primary motivations behind switching technology from bipolar transistors to MOSFETs is that the low power consumption of CMOS circuits along with small size makes integration possible.MOSFETs combined with technology scaling made the IC industry successful because of the reduced power, reduced area, increased speed, and low cost per chip
This paper investigated the scope of various configurations of DGMOSFETs with circuit co-design for ultra-low power radio frequency identification (RFID)
It demonstrated that DGMOSFETs are more promising for future ultra-low power systems in comparison to bulk CMOS
Summary
One of the primary motivations behind switching technology from bipolar transistors to MOSFETs is that the low power consumption of CMOS circuits along with small size makes integration possible. There is an increasing class of applications like portable electronics, micro sensors, radio frequency identification (RFID), and implantable biomedical devices, which demand ultra-low power consumption and prolonged battery lifetime All of these concerns on power reduction motivated the designers to come up with power reduction methods such as supply voltage scaling [1,2], switching activity reduction [3,4], architectural techniques of pipelining and parallelism, computer aided design (CAD) techniques for device sizing and interconnect [5,6], logic optimization [7,8], etc.
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