Abstract
This paper presents the design and simulation of four basic Low Noise Amplifier topologies based on 180nm Silicon technology. A common source stage with inductive degeneration, a resistive feedback, a folded cascode and a cascode stage has been designed, simulated and the performance has been analyzed. The LNA's are designed to be stable in the 2–3GHz. Of the four topologies the cascode stage has a high gain of 19.84dB and a very low Noise Figure (NF) of 0.59dB at 2.5GHz and at a supply voltage of 2.5V. The cascode stage has a P1dB of −17.76dBm and IIP3 of −2.49dBm. The power consumption of the circuit is 18.875mW. The simulations are done in cadence virtuoso SpectreRF. The cascode stage with very low Noise figure and good gain can be used for wireless applications such as Global Positioning System (GPS), Wireless LAN, WCDMA etc.
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