Design and analysis of buffered crossbars and banyans with cut-through switching

Abstract

The design and approximate analyses of discrete time buffered crossbar and banyans with cut-through switching are presented. The crossbar switches can contain either (1) input FIFO queueing, (2) input “bypass” queueing where the FIFO discipline is relaxed, (3) a novel scheme called “restricted output queueing” where the number of simultaneous arrivals to an output queue is upper bounded, or (4) a novel combination of input FIFO and restricted output queueing. An analysis for the delay distribution of a packet leaving the network is presented. It is shown that restricted output queueing (or combined input and restricted output queueing) can rival the performance of pure output queueing, while requiring far less hardware; typically, limiting the number of simultaneous arrivals to an output queue to 2 or 3 is sufficient to ensure near optimal performance. It is shown that for light to moderate loads, cut-through switching offers significant improvement since most buffers are empty and cut-through occurs often. A comparison indicates that cut-through switching offers larger performance improvements when newer pin-limited GaAs Integrated circuits are used, rather than conventional CMOS or ECL, due to the similarity to bit-serial transmission in the newer and faster ICs with fewer pins.