Design and Analysis of Area and Power Efficient 1-Bit Full Subtractor using 120nm Technology

Abstract

In this paper an area and power efficient 14T 1-bit Full Subtractor design has been presented by using GDI techniques. The proposed 1-bit Subtractor design consist of 7 NMOS and 7 PMOS. For difference output of 1-bit full Subtractor GDI XOR-XNOR module outputs has been used with GDI 2x1 MUX. A GDI XOR- XNOR module has been used which consume less area at 120 nm as compared with the previous XOR-XNOR modules. The proposed GDI 1- bit Full Subtractor design is based on this area efficient 6T XOR- XNOR module. To improve area and power efficiency a cascade implementation of XOR module has been avoided in the used 1-bit GDI Full Subtractor module. Difference block of this 1-Bit Full Subtractor module has been implemented by 8 transistors only. The proposed 1-bit Full Subtractor has been designed and simulated using DSCH 3.1 and Microwind 3.1 on 120nm. Also the simulation of layout and parametric analysis has been done for the proposed 1-bit GDI Full Subtractor design. Power variation with respect to the supply voltage has been performed on BSIM-4 and LEVEL-3 on 120nm. Results show that area consumed by the proposed 1- Bit GDI Full Subtractor is 263.1μm 2 on 120nm technology. At 1.2V input supply voltage the proposed 1-bit GDI Full Subtractor consume 7.697µW power at BSIM-4 and 7.708µW power at LEVEL-3. Also the proposed 1-bit GDI Full Subtractor has been compared with other Subtractor designs by CMOS, TG and PTL logic and the proposed design has been proved both area and power efficient as compared to design by other logics.