Design and Analysis of a Low Power Multi-Threshold CMOS Based ARM926 System

Abstract

Low Power techniques such as multi-voltage islands, voltage scaling and power gating are gaining acceptance to address the need for managing energy and power during run time as well as during standby modes. These design techniques increase the complexity of implementing and analyzing the power network to meet the required average IR drop requirements, transient turn on in-rush (out-rush) currents as well as dynamic voltage drops during runtime. We have designed an ARM926 based SoC that implements the above techniques including a multi-threshold CMOS (MTCMOS) based processor core. To analyze the effects of associated with power gating we have built in, as part of the logic design, a system that uses the scan chain based network to observe the effects of transient currents on the virtual power network on state retention. The system can also be used to check the integrity of the retention latches when the design has been powered off using the MTCMOS network. This paper describes the design techniques and presents the analysis of the energy savings for different modes.