Design and Analysis of a Compact Reversible Ternary Systolic Array

Abstract

Multi-valued logic synthesis is a very promising and affluent research area at present because of allowing designers to build much more efficient computers than the existing classical ones. In this regard, research on ternary logic synthesis has got impetus in the recent years. Many existing literature are mainly perceptive to the realization of efficient ternary reversible processors. This research is based on the design of a reversible systolic array, one of the best examples of the parallel processing, using micro level ternary Toffoli gate. General architecture of the ternary reversible systolic array multiplier is shown along with example. Lower bound for the quantum cost and the garbage outputs in terms of entire circuit entire circuit is calculated here to establish the compactness of the design. Finally, comparative result shown that the proposed circuit outperforms the existing one both in terms of number of gates and Quantum cost analysis.