Design and Analysis of 10-bit, 2 MS/s SAR ADC Using Nonredundant SAR and Split DAC

Abstract

In this paper, the designing and analysis of 10-bit, 2 MS/s Successive Approximation ADC using nonredundant SAR and Split DAC is described. Simulation is performed through Cadence tool using gpdk 180 nm technology. Dynamic range for this architecture is 60.19 dB. The charge redistribution DAC in split capacitor structure has a total capacitance which is 96.87% lesser compared to a usual design. To construct 10-bit successive approximation register analog-to-digital converter (SAR ADC), there are two successive approximation register (SAR) configurations are used. First one is sequencer code register successive approximation register configuration, which needs 20 FFs and thus desires more power consumption and occupies more area. The second one is nonredundant successive approximation register configuration, which needs 10 FFs and some combinational logic, thus requires less power consumption and occupies less area. Hence successive approximation registers ADC implementation using split array DAC and nonredundant SAR structure occupies a smaller area as well as consumes less power. The power consumed by SAR ADC using nonredundant SAR and split DAC is obtained as 81.4721 μW and conventional SAR ADC using sequencer code register SAR and binary-weighted DAC is obtained as 211.1908 μW.