Deposited Thin SiO2 for Gate Oxide on n-Type and p-Type GaN

Abstract

Here, we report on a comparison of two different methods to achieve thin deposited layers for gate oxide on n- and p-type GaN by using plasma-enhanced chemical vapor deposition with silane and tetraethyl orthosilicate precursors. An annealing was performed at for 2 min in ambient as an attempt to improve electrical characteristics. Before and after annealing, capacitors were electrical/physically analyzed by capacitance–voltage (C-V), conductance–voltage, current–voltage, optical microscope, scanning electron microscope, atomic force microscope, and secondary-ion mass spectrometry. Globally, the p-type samples presented higher interface state density and rougher surfaces, and in some C-V measurements, it is possible to observe inversion-like characteristics. The surface roughness also increases after annealing. The interfacial trap density for the different interfaces has been determined. Silane samples exhibit lower than TEOS samples. For n-type, annealed from silane has been found as the sample with the lowest . The annealing on the from silane samples is not so efficient for the p-type with the actually increasing. A discussion on the different diffusion mechanisms in correlation with the electrical results is performed in the last section of this paper.