Depolarization Field in FeFET Considering Minor Loop Operation and Charge Trapping

Abstract

The ferroelectric field-effect transistor (FeFET) is a promising candidate for emerging memory. However, data retention loss is a key issue. One reason for the data retention loss is the depolarization field ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{dep}$ </tex-math></inline-formula> ). In this work, we theoretically investigate <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{dep}$ </tex-math></inline-formula> of ferroelectric transistors with the metal/Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si substrate (MFIS) gate structure considering the minor loop and charge trapping effect at the ferroelectric/interlayer interface. We find that <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{dep}$ </tex-math></inline-formula> increases first and then decreases with the increased interlayer thickness ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${t}_{IL}$ </tex-math></inline-formula> ). The charge trapping phenomenon will decrease <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{dep}$ </tex-math></inline-formula> and make <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${t}_{IL}$ </tex-math></inline-formula> at which <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{dep}$ </tex-math></inline-formula> reaches the peak value larger. To design a ferroelectric transistor considering both the depolarization field and the memory window, different schemes about how to choose suitable interlayer and ferroelectric layer thicknesses in three different regions need to be adopted.