Abstract
The silicon pixel detector of the CMS experiment at CERN will be replaced with an upgraded version at the beginning of 2017 with the new detector featuring an additional barrel- and end-cap layer resulting in an increased number of fully digital read-out links running at 400 Mbps. New versions of the PSI46 Read-Out Chip and Token Bit Manager have been developed to operate at higher rates and reduce data loss. Front-End Controller and Front-End Driver boards, based on the μTCA compatible CMS Tracker AMC, a variant of the FC7 card, are being developed using different mezzanines to host the optical links for the digital read-out and control system. An overview of the system architecture is presented, with details on the implementation, and first results obtained from test systems.
Highlights
The silicon pixel detector of the CMS experiment at CERN will be replaced with an upgraded version at the beginning of 2017 with the new detector featuring an additional barreland end-cap layer resulting in an increased number of fully digital read-out links running at 400 Mbps
Front-End Controller and Front-End Driver boards, based on the μTCA compatible CMS Tracker AMC, a variant of the FC7 card, are being developed using different mezzanines to host the optical links for the digital read-out and control system
A total of 72 AMCs, with 56 being FEDs, 14 Pixel-FECs and 2 Tracker-FECs, distributed over a total of 7 crates,will be required to control and read-out the barrel- and forward pixel detector. 2.2 The CMS Tracker AMC (CTA) The CTA shown in Figure 2, which is a variant of the FC7 card [3], is a full-size, double-width Advanced Mezzanine card holding a Xilinx Kintex 7 FPGA and offering two low-pin-count compatible (LPC) FPGA Mezzanine Card (FMC) slots
Summary
The overall design of the proposed backend electronics for the Phase 1 pixel detector follows a μTCA schema adopted by CMS with some minor modifications to take into account the increased bandwidth requirements of the FEDs towards the central DAQ system in the Phase 1 pixel detector It uses a redundant, dual-star μTCA backplane to distribute clock-, trigger- and fast commands that are received from the central TCDS system via a developed module called AMC13 [4]. A software library called μHAL and IPBUS, the corresponding firmware IP block, are used for control of the AMCs [5]. 400 Mbps read-out “fast I2C” pixel link CCU control link Ethernet control TCDS: clock, trigger
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