Dependence of Short-Circuit Withstand Capability of SiC MOSFETs on Short-Circuit Failure Time

Abstract

The aim of this article is to elucidate the short-circuit failure mechanism of SiC metal–oxide–semiconductor field-effect transistors that cause mechanical failure of the interlayer dielectric adjacent to the gate, to find the relationship between the short-circuit withstand capability and short-circuit failure time, and to classify failure modes by the short-circuit failure time. When the short-circuit failure time is shorter than the critical time, the stresses acting on the interlayer dielectric caused by the thermal expansion of the SiC die exceed the fracture stress limit of the oxide films. Therefore, cracks occur at the interlayer dielectric between the gate and the source. In this case, the short-circuit withstand capability can be predicted by thermal theory because the thermal expansion of the SiC die is determined by the temperature rise. However, when the short-circuit failure time is longer than the critical time, the stresses acting on the interlayer dielectric are less than the fracture stress limit of the oxide films. Thus, the failure mode changes to metallization short mode without causing interlayer dielectric cracks. Thermal stress simulations and experiments ascertain that the stress acting on the interlayer dielectric due to the thermal expansion of SiC varies with the short-circuit failure time, resulting in an altered failure mode.