Dependence of Read Margin on Pull-Up Schemes in High-Density One Selector–One Resistor Crossbar Array

Abstract

This paper reports on comprehensive analytical and numerical circuit analyses on the read margin of the one selector-one resistor (1S1R) resistive-switching crossbar array. These analyses are based on the experimental characteristics of the 1S1R cells and provide a valuable insight into their potential for ultrahigh-density data storage. Three read schemes, namely, one bit-line pull-up (One-BLPU), all bit-line pull-up (All-BLPU), and partial bit-line pull-up (Partial-BLPU), are investigated. In contrast to the One-BLPU scheme, the All-BLPU scheme can realize a large crossbar array of 16 Mb, even when the line resistance is nonnegligible because the effective resistance at the sneak current path is substantially less sensitive to the array size. Additionally, the Partial-BLPU scheme can be used to reduce power consumption if random read access is desirable. Finally, the effects of line resistance on the read and write margins are discussed.