Dependence of junction depth and sheet resistance on the thermal budget in the low temperature pre-stabilization regime

Abstract

According to the 2001 International Technology Roadmap for Semiconductors (ITRS) one of the key challenges for source/drain extension technology at the 100 nm technology node and beyond is to produce a junction in the range of a few tens of nanometers with low sheet resistance values. To achieve the requirements of the ITRS, a deep understanding of the diffusion, activation and the dopant-defect interaction is necessary. In this paper the temperature-time profile of spike anneals is varied. The temperature of the pre-stabilization step was set between 600dC and 800dC for 10 s. The pre-stabilization step was followed by a constant spike-annealing condition to achieve high electrical activation, and for reference each pre-stabilization condition was also used to process wafers without additional spike-annealing. The effects of these variations in the thermal budget in the low temperature regime were evaluated for the implant species 11B+ and 49BF2+ and for diverse implant energies and doses. All the data are analyzed and discussed with respect to the junction depth versus sheet resistance figure. With the pre-stabilization at 650dC for 10 s followed by the spike anneal the best results with respect to junction depth and sheet resistance are achieved.