Demonstration system of the HGTD peripheral electronics boards for ATLAS phase II upgrade

Abstract

Prior to the prototype of the HGTD peripheral electronics boards (PEB) for the ATLAS phase II upgrade during the HL-LHC, a demonstration system has been developed to verify some uncertain aspects and facilitate many related studies and tests. Benefiting from its modular design, the system can not only make it possible to replace malfunctioning chips but also be compatible with commercial chips when the key chips are not available. With two lpGBT chips and one VTRx+ deployed, the system can support up to 14 front-end modules, one downstream (2.56 Gbps) and two upstream (10.24 Gbps) optical links. In addition, a module emulator was designed to mimic the front-end modules in both dimension and functionality since real modules are still in development. With a FPGA-based board uFC as the DAQ board, the system was extensively tested and showed very good performance, in particular, the uplink and downlink paths were successfully established and the bit error rates of the data transmission are less than 1×10−14.