Abstract
A functional demonstration of bit-interleaving TDM downstream protocol for passive optical networks (Bi-PON) is reported. The proposed protocol presents a significant reduction in dynamic power consumption in the customer premise equipment over the conventional TDM protocol. It allows to select the relevant bits of all aggregated incoming data immediately after clock and data recovery (CDR) and, hence, allows subsequent hardware to run at much lower user rate. Comparison of experimental results of FPGA-based implementations of Bi-PON and XG-PON shows that more than 30x energy-savings in protocol processing is achievable.
Highlights
As the demand for network equipment keeps growing exponentially, power consumption of network equipment is expected to follow, knowing that the dynamic power consumption of a CMOS circuit is proportional to its operating frequency and switching activity [1]
In a passive optical networks (PONs), an optical line terminal (OLT) at the central office is connected to a number of optical network terminations (ONTs) at the customer premises, typically 32 to 128, over a shared fiber plant
Results reported in this paper focus on the International telecommunication union (ITU-T) branch TDM protocol, namely XG-PON, the concept proposed here can be generalized to the IEEE PON protocols
Summary
As the demand for network equipment keeps growing exponentially, power consumption of network equipment is expected to follow, knowing that the dynamic power consumption of a CMOS circuit is proportional to its operating frequency and switching activity [1]. To cope with the increasing bandwidth demand, these protocols have evolved with a higher line rate [4, 5]. These “super-charged” protocols, suffer from the problem of energy inefficiency which is inherited from their predecessors. The third section describes a newly proposed bit-interleaving TDM protocol, namely Bi-PON [6]. The Bi-PON protocol is discussed in more detail and the architecture of the Bi-PON ONT is disclosed to better explain how the protocol facilitates considerable energy savings to be realized. Experimental results with our recently developed bit-interleaving CDR (Bi-CDR) ASIC [8] are compared with XG-PON and an FPGA-based implementation of Bi-PON
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