Demonstration of Ge CMOS inverter and ring oscillator with 10 nm ultra-thin channel

Abstract

Ge is considered as a promising candidate to continue the Moore's law in post-Si technology, due to its high and balanced carrier mobilities, low thermal budget process and good compatibility with Si. Great efforts have been spent on developing the Ge MOSFET technology and great advancements have been accomplished [1–4]. Recently, by using a novel dry etching process, the recessed channel structure has been successfully integrated into the Ge MOSFET processes on the Ge on insulator (GeOI) substrate [5], providing good gate electrostatic control. Based on the same technique, Ge CMOS devices and circuits have been demonstrated [6]. In this work, we further scale the channel thickness (T ch ) from 25 nm down to 10 nm. Both n- and p- MOSFETs, together with CMOS inverters and ring oscillators, are demonstrated with channel lengths (L ch ) from 100 to 50 nm. An oscillation frequency of 64 MHz is achieved in an 80 nm L ch 9-stage ring oscillator at V DD of 2.2 V. To study the channel thickness dependences, both MOSFETs and CMOS inverters with various T ch of 10 nm (this work), 15 and 25 nm (previously work [5]) are compared, indicating that thinner channels provides much improved immunity from the short channel effects (SCEs).