Abstract
We have been developing Josephson/CMOS hybrid memories, where decoders and memory cell arrays are composed of CMOS devices and bit-line current sensors are made by Josephson circuits. In our previous study we reported a fully functional 64-kb CMOS static RAM for the hybrid memory, which includes CMOS differential amplifiers with 40-mV voltage inputs. In this paper we demonstrate a fully functional 64-kb Josephson/CMOS hybrid memory, which is composed SFQ input/output circuits using the AIST Nb standard process and a CMOS static RAM using the Rohm 180 nm CMOS process. All input data, are inputs to the hybrid memory as SFQ signals in the system. The total access time was measured to be about 1.69 ns.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
