Delta-sigma demodulator with large oversampling ratio using the one-hot residue number system

Abstract

A residue number system-based delta-sigma demodulator is presented which demonstrates a significant improvement in oversampling ratio in comparison with equivalent binary designs. The second order design employs a two-stage cascade architecture with two-level internal and four-level output quantization. Analytical estimates show at least a 60% improvement in OSR over binary number system-based designs. Furthermore, latency estimates for a pipelined version show a 70% decrease below binary. These benefits are made possible by the use of the one-hot residue number system, which allows addition and multiplication to be performed equally quickly and simply using barrel shifters and wire transposition. An example implementation of the design is also presented in an Altera 7256 CPLD.