Delayed quadratic buck converter

Abstract

Nowadays, the microprocessors family normally require for the input source not only low voltage but also high current. There exists an increasing necessity for developing new applied techniques on topologies and control strategies, which may be able to fulfil such requirements. Although a considerable amount of applications use the conventional buck converter for step-down for DC/DC conversion, when a high step-down conversion is required is a much better choice to implement the quadratic buck converter (QBC); however, the problem for obtaining a high step-down conversion at wide duty ratio still remains. This document proposes the delayed quadratic buck converter, which offers a very high-step-down dc–dc conversion with a wide duty cycle. The QBC is modified in its topology by adding an inductor, which allows us to obtain for the duty cycle a higher increment than this normally obtained by a quadratic one. Converter behaviour and analysis are illustrated. Experimental results are also shown for a conversion from 36 to 1.5 V and an output power of 20 W.