Delay-time modelling and critical-path verification for cmos digital designs

Abstract

A new switch-level critical-path verifier for cmos digital circuits is presented. The signal flow through mos transistors is determined by combining the designer's tag with a set of direction-derivation rules, and the delays are evaluated on a stage-by-stage basis. The paper uses a semianalytic cmos delay-time model that takes into account the configuration ratio, the input waveform slope and the load condition. This model is derived from the optimally weighted switching peak current, which is, in turn, derived from the Shichman-Hodges' DC equations. The delay equations are computationally effective, and the error is found to be typically within 10% of the spice results. A novel methodology for reporting multiple paths, called a modified depth-first search with predictor, is investigated. In comparison with the conventional method without predictor, it requires much less CPU time.