Delay testing considering crosstalk-induced effects

Abstract

Increased noise/interference effects, such as crosstalk, power supply noise, substrate noise and distributed delay variations lead to increased signal integrity problems in deep submicron designs. These problems can cause logic errors and/or performance degradation and must be addressed both in the design for deep submicron and testing for deep submicron phases. Existing delay testing techniques cannot capture the effects of noise on the cell/interconnect delays. In this paper, we address the problem of delay testing considering crosstalk-induced delay effects. We propose solutions for target fault selection and pattern generation. The key elements of our strategy are performance sensitivity analysis with respect to crosstalk noise and a genetic algorithm (GA) based vector generation technique. The role of performance sensitivity analysis is to consider the effects of crosstalk noise during the target fault selection process. Next, for each selected fault consisting of a path and a set of crosstalk noise sources interacting with the path, we apply our iterative GA-based pattern generation process. Our goal is to derive a test that produces a large crosstalk-induced delay effect on the given path. Our technique allows consideration of any number of coupling sources along the target path. Due to its flexibility, efficiency and scalability, the technique can be applied to large circuits.