Delay sensing for parametric variations and defects monitoring in safety-critical applications

Abstract

The impact of parametric variations on digital circuit performance is increasing in nanometer ICs, namely of PVT (Process, power supply Voltage and Temperature) variations. Moreover, circuit aging also impacts circuit performance, especially due to NBTI (Negative Bias Temperature Instability) effect. A growing number of physical defects manifest themselves as delay faults (at production, or during product lifetime). On-chip, on-line delay monitoring, as a circuit failure prediction technique, can be an attractive solution to guarantee correct operation in safety-critical applications. A novel delay sensor (to be selectively inserted in key locations in the design and to be activated according to user's requirements) is proposed, and a 65 nm design is presented. The nanometer CMOS sensor is programmable, allowing delay monitoring for a wide range of delay values. The proposed sensor has been optimized to exhibit low sensitivity to PVT variations. Simulation results show that the sensor is effective on identifying abnormal delays, due to NBTI-induced aging and to resistive bridging defects.