Delay Optimized Binary to BCD Converter for Multi-operand Parallel Decimal Adder

Abstract

Decimal arithmetic is receiving greater attention due to its applications in banking and internet-based sectors. Several algorithms have been introduced for Multi-operand addition. A mixed approach of having binary adders followed by binary to BCD converter is showing better performance compared to binary adders with correction logic in intermediate stages. Adder circuits form the basis of our computing. Multiplication and division algorithms are also based on the adder circuits. Thus designing fast Multi-operand parallel adders is receiving greater interest by researchers. BD converters that are the final blocks of the adder circuits have gained a lot of importance highlighting the need to have an efficient BD converter as critical for improvised adder architectures. This paper proceeds with the mixed approach and it considers the special case of 8 operand decimal addition which is done using binary CSA structure and proposes a BD converter for 7-bit binary number that is efficient in terms of area and delay when compared to the existing designs. The power delay product of our design is 27% more efficient than existing designs.