Delay Modeling for Power Noise and Temperature-Aware Design and Test of Digital Systems

Abstract

The implementation of complex, high-performance functionalities in low-power nano-CMOS technologies faces significant design and test challenges related to the increased susceptibility to environmental or operation-dependent disturbances, process variations or emerging defect types. This paper describes the application of semi-empirical propagation delay variation models to support the design and test of low-power nanometer digital circuits, taking into account these challenging issues. Results are presented demonstrating that the models provide designers and test engineers with a powerful tool to analytically account for all effects leading to delay faults. They can be used to define parametric delay tests, as well as to design circuits with increased robustness to delay faults under low-power operation. Its derivation and application can be easily automated, allowing them to be integrated in standard flows.