Delay metric for on-chip RLCG interconnect for arbitrary input

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In order to accurately model high frequency effects inductance had been taken into consideration. Earlier only the delay caused due to the presence of gates was considered to be an important issue, but now with decreasing feature size and increasing complexity ,on chip interconnect delay has acquired prominence for incremental performance-driven layout synthesis. We develop a novel analytical delay model, for RLCG interconnect lines that in addition to preserving the effectiveness of previous RLCG interconnect models, improves the accuracy for deep submicron technologies that are used at higher frequencies. In this paper we have put forward an analytical model, which could accurately capture the on chip interconnect delay. We develop a novel analytical model based on the first and second moments of the interconnect transfer function when the input is arbitrary signal. Delay estimate using our first moment based analytical model is within 3% of SPICE-computed delay, and model based on first two moments is within 2% of SPICE, across a wide range of interconnects parameter values.