Delay insertion method in clock skew scheduling

Abstract

This paper describes a delay insertion method that improves the efficiency of clock skew scheduling. Clock skew scheduling is performed on synchronous circuits in order to improve the performance of a circuit; most often by permitting the circuit to operate at a lower clock period or by increasing the tolerance of the circuit against secondary order effects and process parameter variations. With clock skew scheduling, the original circuit topology is preserved while the clock distribution network is modified to satisfy an optimal clock schedule (set of clock signal arrival delays). The work presented here studies a circuit modification technique requiring systematic delay insertion within the circuit logic (delay insertion method) in order to improve the minimum clock period achieved through clock skew scheduling. The proposed delay insertion method is defined and demonstrated on both edge-triggered and level-sensitive synchronous circuits leading to average clock period improvements of 9% and 10%, respectively, over standard clock skew scheduling algorithms. Overall, the clock period improvements over zero clock skew, flip-flop based circuits are improved to 34% on average, both for the edge-triggered and level-sensitive designs of ISCAS'89 benchmark circuits.