Delay bounds for combined input–output switches with low speedup

Abstract

The speedup of a switch is the factor by which the switch, and hence the memory used in the switch, runs faster compared to the line rate. In high-speed switches, line rates are already touching limits at which memory can operate. In this scenario, it is very important for a switch to run at as low a speedup as possible. In the past, it has been shown that 100% throughput can be achieved for any admissible traffic for an input queued (IQ) switch [IEEE Trans. Commun. 47 (8) (1999) 1260; The throughput of data switches with and without speedup, in: Proceedings of the IEEE INFOCOM’00, vol. 2, Tel Aviv, Israel, March 2000, pp. 556–564] at speedup 1. This gives finite average delays but does not guarantee control on packet delays. In [IEEE J. Sel. Areas Commun. 17 (6) (1999) 1030], authors show that a combined input–output queued (CIOQ) switch can emulate perfectly an output queued (OQ) switch at a speedup of 2 and, thus, control the packet delays. This motivates the study of possibility of obtaining delay control at speedup less than 2. To guarantee optimal control of delays for a general class of traffic, as shown in [3], speedup 2 is necessary. Hence, to obtain control of delays at lower speedup, we need to restrict the class of arrival traffics. In this paper, we study the speedup requirement for a class of admissible traffic, which we will denote as (1, nF)-regulated traffic, with parameters n and F. We obtain the necessary speedup for this class of traffic. Further, we present a general class of algorithms working at the necessary speedups and providing bounded delays.