Delay bounds based constraint distribution method

Abstract

Transistor sizing is one of the easiest post-processing transforms used to optimise critical paths to fill timing specifications. Most transistor sizing tools, based on nonlinear mathematical programs present high execution times and do not give an indication of the design space explored by the optimisation step. A fast transistor sizing method to address the problem of delay constraint distribution on a CMOS combinatorial path is defined. This method is based on a closed form model of the propagation delay that incorporates the effect of input slew rates on gate delays. The design space is characterised with a technique that allows the determination of the feasible delay bounds of any combinational paths. Then two different constraint distribution methods are defined that are compared to the equal delay distribution and to an industrial tool based on the Newton-Raphson-like algorithm. Validation is obtained on a 0.25 µm process by comparing the different constraint distribution techniques on various benchmarks.