Degradation of polysilicon TFTs during dynamic stress

Abstract

The authors examine the degradation of polysilicon thin film transistors (TFTs) during dynamic voltage stress, using conditions which simulate those experienced by TFTs in digital circuits. It is shown that the manner in which n-channel polysilicon TFTs degrade under typical circuit switching conditions differs from that observed during DC stress. In particular, after dynamic stress, current pinching and asymmetric characteristics are observed, neither of which are observed after DC stress. P-channel TFTs, on the other hand, degrade in a similar manner during both static and dynamic stress. Both n- and p-channel TFT degradation rates are typically much slower under dynamic conditions than under DC stress for a given stress voltage, partly due to the intermittent nature of the stress and partly due to the fact that the worst-case DC conditions do not normally arise in circuit operation. The degradation of n-channel TFTs can be reduced by minimizing transition times, introducing an additional consideration for circuit design. >