Degradation and lifetime estimation of n-MOS SLS ELA polycrystalline TFTs during hot carrier stressing: effect of channel width in the region Vth ⩽ VGS,stress ⩽ VDS,stress/2

Abstract

The voltage bias stress induced degradation of sequential lateral solidification (SLS) polysilicon thin film transistors (TFTs) is studied. The aim of this work is the investigation of the types of damage arising from the electrical stressing in the gate voltage range around Vth ⩽ VGS,stress ⩽ VDS,stress/2 and for different drain-bias voltages. It is shown that the drain on-current variation (%) with stressing time for a defined gate voltage obeys a power–time-dependent law of the form Atn. The parameters A and n of this law were determined in order to gain insight on degradation mechanisms in different stress regimes and to estimate the time to failure of our devices. Devices with different channel widths were compared, and their lifetime to failure was extracted. It was found that the magnitude of stress was lower for devices with narrower channel widths. By monitoring the threshold voltage variation and the percentage change of transconductance maximum in the linear regime of operation, it was verified that the threshold voltage degradation was mainly due to the contribution of Gm,max to Vth rather than severe carrier trapping.