Degradation and Full Recovery in High-Voltage Implanted-Gate SiC JFETs Subjected to Bipolar Current Stress

Abstract

Electron-hole-recombination-induced stacking faults (SFs) have been shown to degrade the electrical characteristics of SiC power pin and MPS diodes and DMOSFETs with thick drift epitaxial layers. In this letter, we investigate the effects of bipolar current stress on the electrical characteristics of ion-implanted gate vertical-channel JFETs with 100-μm drift epilayers. JFETs are stressed at a fixed gate-drain dc bipolar current density of 100 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> for 5 h. Several JFETs exhibit severe forward gate-drain voltage degradation, while others show intermediate or no degradation. As degradation under bipolar current stress is caused by basal plane dislocation (BPD)-induced SF formation and expansion, the differences in degradation severity are attributed to the nonuniform BPD concentrations in the JFETs' drift epitaxial layers. Forward/reverse gate-source, transfer, reverse gate-drain, and blocking voltage JFET characteristics exhibit no degradation with bipolar stress. Forward gate-drain voltage and on-state conduction degrade in affected JFETs. The degradations are fully reversed by annealing at 350 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C for 96 h, while nondegraded electrical characteristics remain unaffected by the annealing. These results suggest that elevated-temperature bipolar JFET operation can proceed without BPD-induced SF-related degradation. In the absence of BPDs, bipolar operation does not impact JFET electrical characteristics.