Degas Module Thermal Architecture, Variable Wafer Delays, and Throughput, Productivity, and Consistency in Fan-Out Packaging Barrier/Seed Layer PVD

Abstract

The standard architecture for vacuum-based processing equipment in the commercial semiconductor and advanced packaging industries is the cluster tool architecture, or some variant of it. For fan-out packaging barrier/seed layer sputter deposition, reconstituted mold compound wafers or panels see a degas chamber, a pre-clean chamber, a Ti PVD chamber, and a Cu PVD chamber, along with the loading/unloading stations themselves. Our industry has worked on optimizing cluster tool wafer transport and process flow scheduling in order to optimize throughput in central wafer handling systems. However, we are still resigned to cluster tools forever operating in two regimes: at best, in the robot–limited region but, more commonly, in the process–limited region, with its lower associated throughput. There is also a second detail to consider in cluster tool processing: wafer delays. Wafer delays, either in the PVD tool process chambers, or in the tool transport, take away from system throughput, and potentially introduce subtle process variations as well. We report here on the design and operation of a continuous transport degas module, part of the set of continuous transport process modules that contrast with the standard process module configurations of robot pick-and-place vacuum cluster tools. As the lead process module in a carrier-based linear transport PVD system configured for fan-out packaging barrier/seed layer deposition, the continuous transport degas effectively sets up all subsequent process modules in the linear transport PVD tool to perform robust, regulated, and highly repeatable process sequences in which neither fan-out wafers nor fan-out panels experience transport-related wafer delays, variable or not. This continuous process architecture should aid PVD process consistency, as it eliminates one potential source of subtle process variations, that of wafer transport variability.