Defect related effects on the reliability and performance of an embedded DRAM cell designed with MOSFETs with alternative gate dielectrics

Abstract

The design of an embedded DRAM based on MOSFETs with alternative gate dielectrics is presented and analysed. Design and evaluation of NMOS devices with high-k dielectric gate insulators and DRAM circuits took place. Reliability parameters of the NMOS devices constructed with (Ba,Sr)TiO3 gate dielectrics were examined. A 90 nm technology model and the BSIM4 Spice equations were used in order to derive the device behaviour and the DRAM circuit performance. The simulation revealed low output currents for the MOSFETs and higher decay times for the DRAM circuits constructed using the devices with the alternative gate dielectrics.