Defect engineering in annealed n-type GaAs epilayers using SiO2/Si3N4 stacking layers

Abstract

We have used SiO2/Si3N4 stacking layers to control the creation of defects in rapid thermally annealed epitaxial GaAs layers. Annealing at 900 °C introduces three electron traps S1 (Ec−0.23 eV), S2 (Ec−0.53 eV), and S4 (Ec−0.74 eV) in SiO2/n-GaAs. The concentrations of S1 and S4 decreased by factors of ∼28 and ∼19, respectively, in Si3N4/SiO2/n-GaAs. The overlap of a hole trap with the S2 peak in Si3N4/SiO2/n-GaAs results in an apparent decrease in the concentration of S2 by over two orders of magnitude. The lower concentration of defects in the region probed by deep level transient spectroscopy is explained by the tensile stress which the Si3N4 layer imposes on the structure during annealing. In addition to S1 and S4, hole traps H1 (Ev+0.28 eV) and H2 (Ev+0.42 eV) are observed in Si3N4/n-GaAs and SiO2/Si3N4/n-GaAs, respectively. The concentration of defects is larger by ∼1.5 times in the latter structure. SiO2/Si3N4 stacking layers can, therefore, be used to achieve spatially selective modification of GaAs-based structures using defect engineering.