Defect Characterization of PEALD High-k ZrO2Films Fabricated on III–V Materials

Abstract

To enable scalable MOSFET technology in III–V semiconductor platforms, high quality semiconductor-oxide interfaces are essential. In this paper, a novel low-temperature plasma-enhanced atomic layer deposition (PEALD) technique was applied to deposit nanoscale high-k dielectrics on several III–V substrates, including InP, GaAs, InAs, and GaN. Approximately 7 nm of ZrO2 was grown and patterned to form MOSCAP structures, which were subsequently analyzed through electrical characterization to evaluate dielectric and interface quality. The oxide films fabricated were found to have interface trap densities ranging from 1010 – 1013 eV−1 cm−2, and showed high capacitance densities ( $\boldsymbol {\sim 2.5}~{\boldsymbol \mu }\text{F}$ /cm2). GaN and InP MOSCAPs with ZrO2 dielectric layers were found to have gate currents in line with direct tunneling phenomena and MOS mobilities approaching that of doped bulk semiconductors. Scaled InP MOSFET devices using these experimental values were also simulated using an optimized device structure.