Defect analysis of strained silicon on thin strain-relaxed buffer layers for high mobilitytransistors

Abstract

The electrical activity of defects present in strained silicon (SSi) on thin strain-relaxedSi1−xGex buffer layers (SRBs) is evaluated using deep submicron CMOS compatiblen+/p andp+/n shallowjunctions. Strain relaxation has been achieved here by introducing a thin carbon-rich layer in an otherwiseuniform Si0.78Ge0.22 epitaxial layer, resulting in an SRB thickness of 248 or 348 nm andprocessing compatible threading dislocation densities in the range of a few106 cm−2. From a combination of electrical measurements (current– and capacitance–voltage;microwave absorption (MWA) recombination lifetime) and microscopic techniques(electron-beam-induced current; emission microscopy), it is concluded that generationcentres associated with the C layer can play an important role. Their electrical activityis shown to depend strongly on the relative position of the C-doped layer withrespect to the junction depth. The type of well dopant (implantation) also hasa strong impact on the electrical activity of the different defect types presentin the epitaxial layers. It is generally found that the 348 nm junctions show alower reverse current at practical operation temperatures and voltages, while thep+/n diodes exhibit a better performance compared with theirn+/p counterparts.