Deeply scaled VLSI analog transistor design and optimization

Abstract

Analog performance optimization of 14nm node FinFET has been studied using calibrated Sentaurus TCAD tools. Graded channel (GC) design, source/drain parasitic reduction and high mobility channel material have been used to improve the external transconductance (g m_ext ) of FinFET. Graded channel design induces a more uniform inversion charge density and velocity distribution along the channel, which increases the average carrier velocity. An optimized doping profile in the gate underlap region can reduce the gate underlap parasitic resistance from 2000Ω/Fin to 365 Ω/Fin. Combining the improved average carrier velocity and reduced parasitic resistance, the extrinsic trans-conductance (g m_ext ) of Si/SiGe GC 14nm FinFET is 2x of that in the experimental homojunction 14nm FinFET. A further 50% improvement in g m_ext has been observed by using high mobility GaAs/InGaAs as the channel material of GC FinFET.