Abstract
A fabrication process has been developed for fully planarized Nb-based superconducting interlayer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of etched contact holes in the interlayer dielectric it employs etched and planarized Nb pillars (studs) as connectors between adjacent wiring layers. Detailed results are presented for one version of the process that utilizes Nb/Al/Nb trilayers for each wiring layer instead of single Nb wiring layers. Nb studs are etched in the top layer of the trilayer to provide vertical connections between the wires etched in the bottom layer of the trilayer and the next wiring layer that is also deposited as a Nb/Al/Nb trilayer. This technology makes possible a dramatic increase in the density of superconducting digital circuits by reducing the area of interconnects with respect to presently utilized etched contact holes between superconducting layers and by enabling the use of stacked vias. Results on the fabrication and size dependence of electric properties of Nb studs with dimensions near the resolution limit of 248-nm photolithography are presented in the normal and superconducting states. Superconducting critical current density in the fabricated stud-vias is about 0.3 A μm−2 and approaches the depairing current density of Nb films.
Highlights
In order to realize the tremendous advantages of superconducting digital integrated circuits over semiconductor circuits in speed and reduction of energy dissipation [1], their integration scale must be increased from its current medium level to very large scale integration (VLSI) levels and beyond
This limits the minimum size of contact holes to ~ 0.5 μm, as it becomes difficult to achieve reliable contacts with sufficient superconducting critical currents in smaller holes, because increasing their aspect ratio leads to poor step coverage and formation of voids
We found that this process allowed us to form Nb stud-vias with sizes down to our photolithography resolution limit (~250 nm) and with superconducting critical current density approaching the depairing critical current density of Nb. 2
Summary
In order to realize the tremendous advantages of superconducting digital integrated circuits over semiconductor circuits in speed and reduction of energy dissipation [1], their integration scale must be increased from its current medium level to very large scale integration (VLSI) levels and beyond This requires increasing the density of elemental switching devices – Josephson junctions (JJs) – by several orders of magnitude, from the present density of ~ - JJs per cm to - JJs/cm, with a corresponding increase in the density of interconnects (Josephson transmission and passive transmission lines) and other passive components (inductors, resistors, vias). Sloping the contact walls by usual methods to improve step coverage becomes more difficult with the transition to deep-UV lithography which favors near-vertical photoresist profiles
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