Abstract
Deep Level Transient Spectroscopy (DLTS) studies have been carried out on Au/SiO2/InP Metal–Oxide–Semiconductor (MOS) diodes. Majority and minority carrier traps have been observed for the room temperature SiO2 deposited samples. The effect of substrate temperature during SiO2 deposition has been analysed using DLTS. It has been observed that the minority carrier trap is removed while SiO2 deposition is carried out at an elevated temperature. The detected traps have been analysed under different reverse bias values to distinguish between the bulk and interface traps.
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