Deep Learning-assisted Scan Chain Diagnosis with Different Fault Models during Manufacturing Test

Abstract

Manufacturing of integrated circuits at the smaller technology nodes leads to several defects in them that must be screened and appropriately diagnosed for minimization of cost overruns. A substantial portion of the functional failures during the process of manufacturing test is often attributed to the defects inside the scan chains. With the advancements in the digital test technologies, almost every chip is manufactured with in-built pattern compression infrastructure. This exacerbates the problem of scan chain diagnosis from the collected failure traces. In this work, an automated methodology to perform this diagnosis in the presence of multiple faults is proposed. Deep learning is utilized to predict the probable candidate locations given the compressed scan chain response. Experiments have been performed on different fault models. Experimental results indicate that the proposed methodology is able to perform the diagnosis with a success rate of approximately 80-100%.