Deep Insight into DC/RF and Linearity Parameters of a Novel Back Gated Ferroelectric TFET on SELBOX Substrate for Ultra Low Power Applications

Abstract

In this manuscript, a novel back gated ferroelectric heterojunction TFET on SELBOX substrate (BG-Fe-HJ-STFET) has been proposed. Ferroelectric oxide is considered as gate dielectric material along with SiO2 in a vertical gate stacked manner in the proposed TFET with SELBOX (BG-Fe-HJ-STFET) to improve overall sub-threshold performance of the device. The proposed TFET (BG-Fe-HJ-STFET) is found to achieve a lower sub-threshold swing value of 38.6 mV/decade (below the Boltzmann limit of 60 mV/decade) compared to the SELBOX TFET without ferro dielectric structure (BG- HJ-STFET). Different RF figures of merit such as cut-off frequency, transit time and gain-bandwidth product (GBP) are thoroughly investigated and comparison study is performed for both the TFETs presented for study. Further, the linearity figure of merits (FOMs) like VIP2, VIP3, IIP3, IMD3, and 1-dB compression point has been analyzed for both the TFETs under study. Result shows that the proposed TFET with ferro dielectric gate material (BG-Fe-HJ-STFET) outperforms the SELBOX TFET without ferro dielectric gate material (BG-HJ-STFET) in all aforementioned aspects. Performance analysis is carried out using Silvaco TCAD tool for both TFETs structures.